PINPER=0, EN=0, CAPTURE=0, OFFEN=0, SLAVE=0, PEREN=0, OFFRST=0
Timer Control Register
| EN | Enable timer 0 (0): The timer stops at the current value. 1 (1): The timer starts incrementing. |
| OFFEN | Enable one-shot offset event 0 (0): Disable. 1 (1): The timer can be reset to zero when the given offset time is reached (offset event). The bit is cleared when the offset event is reached, so no further event occurs until the bit is set again. Set the timer offset value before setting this bit. |
| OFFRST | Reset timer on offset event 0 (0): The timer is not affected and no action occurs (besides clearing OFFEN) when the offset is reached. 1 (1): If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. |
| PEREN | Enable periodical event 0 (0): Disable. 1 (1): A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. Set the timer period value before setting this bit. Not all devices contain the event signal output. See the Chip Configuration details. |
| PINPER | no description available 0 (0): Disable. 1 (1): Enable. |
| RESTART | Reset timer |
| CAPTURE | Capture timer value 0 (0): No effect. 1 (1): The current time is captured and can be read from the ATVR register. |
| SLAVE | Enable timer slave mode 0 (0): The timer is active and all configuration bits in this register are relevant. 1 (1): The internal timer is disabled and the externally provided timer value is used. All other bits, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. |